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<div class="title">xsecure_aes_core_hw.h File Reference</div>  </div>
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<a name="details" id="details"></a><h2 class="groupheader">Overview</h2>
<div class="textblock"><p>This file contains AES core hardware definitions of versal. </p>
<pre>
MODIFICATION HISTORY:</pre><pre>Ver   Who  Date        Changes
</p>
<hr/>
<p>
4.0   vns  03/21/19 Initial release
4.2   vns  02/10/20 Added efuse cache DPA mask register address and mask
4.3   ana  06/04/20 Added XSECURE_AES_MODE_DEC macro
      kpt  08/06/20 Added XSECURE_AES_KEY_DEC_RESET_MASK macro
      am   09/24/20 Resolved MISRA C violations
      har  10/12/20 Addressed security review comments
4.5   har  03/02/21 Added register offset for AAD
4.6   har  07/14/21 Fixed doxygen warnings
5.3   kpt  11/28/23 Added XSECURE_AES_KEY_CLEAR_PUF_RED_EXPANDED_KEYS_MASK</pre><pre></pre> </div><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:a032b21f266f931960dc0fab1c6df15ca"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xsecure__aes__core__hw_8h.html#a032b21f266f931960dc0fab1c6df15ca">XSECURE_AES_KEY_SEL_OFFSET</a>&#160;&#160;&#160;(0x00000004U)</td></tr>
<tr class="memdesc:a032b21f266f931960dc0fab1c6df15ca"><td class="mdescLeft">&#160;</td><td class="mdescRight">AES_KEY_SEL register offset.  <a href="#a032b21f266f931960dc0fab1c6df15ca">More...</a><br/></td></tr>
<tr class="separator:a032b21f266f931960dc0fab1c6df15ca"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aafd28b72f9ee5ce4fa83e3e27d3410d8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xsecure__aes__core__hw_8h.html#aafd28b72f9ee5ce4fa83e3e27d3410d8">XSECURE_AES_SOFT_RST_OFFSET</a>&#160;&#160;&#160;(0x00000010U)</td></tr>
<tr class="memdesc:aafd28b72f9ee5ce4fa83e3e27d3410d8"><td class="mdescLeft">&#160;</td><td class="mdescRight">AES_KEY_SOFT_RST register offset.  <a href="#aafd28b72f9ee5ce4fa83e3e27d3410d8">More...</a><br/></td></tr>
<tr class="separator:aafd28b72f9ee5ce4fa83e3e27d3410d8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7af708c3a88350c17329dc3d43ec674a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xsecure__aes__core__hw_8h.html#a7af708c3a88350c17329dc3d43ec674a">XSECURE_AES_IV_0_OFFSET</a>&#160;&#160;&#160;(0x00000040U)</td></tr>
<tr class="memdesc:a7af708c3a88350c17329dc3d43ec674a"><td class="mdescLeft">&#160;</td><td class="mdescRight">AES_IV_0 register offset.  <a href="#a7af708c3a88350c17329dc3d43ec674a">More...</a><br/></td></tr>
<tr class="separator:a7af708c3a88350c17329dc3d43ec674a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7cb9fb7cebf2d5bbaafe1b724080f6ad"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xsecure__aes__core__hw_8h.html#a7cb9fb7cebf2d5bbaafe1b724080f6ad">XSECURE_AES_IV_3_OFFSET</a>&#160;&#160;&#160;(0x0000004CU)</td></tr>
<tr class="memdesc:a7cb9fb7cebf2d5bbaafe1b724080f6ad"><td class="mdescLeft">&#160;</td><td class="mdescRight">AES_IV_3 register offset.  <a href="#a7cb9fb7cebf2d5bbaafe1b724080f6ad">More...</a><br/></td></tr>
<tr class="separator:a7cb9fb7cebf2d5bbaafe1b724080f6ad"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4eeb401134c2a56c8a82b0cc0eca3f55"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xsecure__aes__core__hw_8h.html#a4eeb401134c2a56c8a82b0cc0eca3f55">XSECURE_AES_KEY_SIZE_OFFSET</a>&#160;&#160;&#160;(0x00000050U)</td></tr>
<tr class="memdesc:a4eeb401134c2a56c8a82b0cc0eca3f55"><td class="mdescLeft">&#160;</td><td class="mdescRight">AES_KEY_SIZE register offset.  <a href="#a4eeb401134c2a56c8a82b0cc0eca3f55">More...</a><br/></td></tr>
<tr class="separator:a4eeb401134c2a56c8a82b0cc0eca3f55"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1df2fa073c3d742d262613a8ea0c0a50"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xsecure__aes__core__hw_8h.html#a1df2fa073c3d742d262613a8ea0c0a50">XSECURE_AES_KEY_DEC_TRIG_OFFSET</a>&#160;&#160;&#160;(0x0000005CU)</td></tr>
<tr class="memdesc:a1df2fa073c3d742d262613a8ea0c0a50"><td class="mdescLeft">&#160;</td><td class="mdescRight">AES_KEY_DEC_TRIG register offset.  <a href="#a1df2fa073c3d742d262613a8ea0c0a50">More...</a><br/></td></tr>
<tr class="separator:a1df2fa073c3d742d262613a8ea0c0a50"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1b97c95e93272e98ea09c3c092c55b4d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xsecure__aes__core__hw_8h.html#a1b97c95e93272e98ea09c3c092c55b4d">XSECURE_AES_KEY_DEC_SEL_OFFSET</a>&#160;&#160;&#160;(0x00000060U)</td></tr>
<tr class="memdesc:a1b97c95e93272e98ea09c3c092c55b4d"><td class="mdescLeft">&#160;</td><td class="mdescRight">AES_KEY_DEC_SEL register offset.  <a href="#a1b97c95e93272e98ea09c3c092c55b4d">More...</a><br/></td></tr>
<tr class="separator:a1b97c95e93272e98ea09c3c092c55b4d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab30dfee1aa8df3062aa88d5a37534eda"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xsecure__aes__core__hw_8h.html#ab30dfee1aa8df3062aa88d5a37534eda">XSECURE_AES_AAD_OFFSET</a>&#160;&#160;&#160;(0x0000006CU)</td></tr>
<tr class="memdesc:ab30dfee1aa8df3062aa88d5a37534eda"><td class="mdescLeft">&#160;</td><td class="mdescRight">AES_AAD register offset.  <a href="#ab30dfee1aa8df3062aa88d5a37534eda">More...</a><br/></td></tr>
<tr class="separator:ab30dfee1aa8df3062aa88d5a37534eda"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a523043b9b41cd0567bf865bc996fa404"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xsecure__aes__core__hw_8h.html#a523043b9b41cd0567bf865bc996fa404">XSECURE_AES_BH_KEY_0_OFFSET</a>&#160;&#160;&#160;(0x000000F0U)</td></tr>
<tr class="memdesc:a523043b9b41cd0567bf865bc996fa404"><td class="mdescLeft">&#160;</td><td class="mdescRight">AES_BH_KEY_0 register offset.  <a href="#a523043b9b41cd0567bf865bc996fa404">More...</a><br/></td></tr>
<tr class="separator:a523043b9b41cd0567bf865bc996fa404"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5004b736c625abef0ca6dada14dcc962"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xsecure__aes__core__hw_8h.html#a5004b736c625abef0ca6dada14dcc962">XSECURE_AES_USER_KEY_0_0_OFFSET</a>&#160;&#160;&#160;(0x00000110U)</td></tr>
<tr class="memdesc:a5004b736c625abef0ca6dada14dcc962"><td class="mdescLeft">&#160;</td><td class="mdescRight">AES_USER_KEY_0_0 register offset.  <a href="#a5004b736c625abef0ca6dada14dcc962">More...</a><br/></td></tr>
<tr class="separator:a5004b736c625abef0ca6dada14dcc962"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a63c576fa7f9355d7dbcaa5c96707c105"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xsecure__aes__core__hw_8h.html#a63c576fa7f9355d7dbcaa5c96707c105">XSECURE_AES_USER_KEY_1_0_OFFSET</a>&#160;&#160;&#160;(0x00000130U)</td></tr>
<tr class="memdesc:a63c576fa7f9355d7dbcaa5c96707c105"><td class="mdescLeft">&#160;</td><td class="mdescRight">AES_USER_KEY_1_0 register offset.  <a href="#a63c576fa7f9355d7dbcaa5c96707c105">More...</a><br/></td></tr>
<tr class="separator:a63c576fa7f9355d7dbcaa5c96707c105"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a06ffdf0ece06ce79887a77fe4544aeb8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xsecure__aes__core__hw_8h.html#a06ffdf0ece06ce79887a77fe4544aeb8">XSECURE_AES_USER_KEY_2_0_OFFSET</a>&#160;&#160;&#160;(0x00000150U)</td></tr>
<tr class="memdesc:a06ffdf0ece06ce79887a77fe4544aeb8"><td class="mdescLeft">&#160;</td><td class="mdescRight">AES_USER_KEY_2_0 register offset.  <a href="#a06ffdf0ece06ce79887a77fe4544aeb8">More...</a><br/></td></tr>
<tr class="separator:a06ffdf0ece06ce79887a77fe4544aeb8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3786274cb3729c28c6e2fffd1444a60d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xsecure__aes__core__hw_8h.html#a3786274cb3729c28c6e2fffd1444a60d">XSECURE_AES_USER_KEY_3_0_OFFSET</a>&#160;&#160;&#160;(0x00000170U)</td></tr>
<tr class="memdesc:a3786274cb3729c28c6e2fffd1444a60d"><td class="mdescLeft">&#160;</td><td class="mdescRight">AES_USER_KEY_3_0 register offset.  <a href="#a3786274cb3729c28c6e2fffd1444a60d">More...</a><br/></td></tr>
<tr class="separator:a3786274cb3729c28c6e2fffd1444a60d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a927532a3705a2716f07c4ddf272b1097"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xsecure__aes__core__hw_8h.html#a927532a3705a2716f07c4ddf272b1097">XSECURE_AES_USER_KEY_4_0_OFFSET</a>&#160;&#160;&#160;(0x00000190U)</td></tr>
<tr class="memdesc:a927532a3705a2716f07c4ddf272b1097"><td class="mdescLeft">&#160;</td><td class="mdescRight">AES_USER_KEY_4_0 register offset.  <a href="#a927532a3705a2716f07c4ddf272b1097">More...</a><br/></td></tr>
<tr class="separator:a927532a3705a2716f07c4ddf272b1097"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a35b6c109e77ba299b89e444694456bb7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xsecure__aes__core__hw_8h.html#a35b6c109e77ba299b89e444694456bb7">XSECURE_AES_USER_KEY_5_0_OFFSET</a>&#160;&#160;&#160;(0x000001B0U)</td></tr>
<tr class="memdesc:a35b6c109e77ba299b89e444694456bb7"><td class="mdescLeft">&#160;</td><td class="mdescRight">AES_USER_KEY_5_0 register offset.  <a href="#a35b6c109e77ba299b89e444694456bb7">More...</a><br/></td></tr>
<tr class="separator:a35b6c109e77ba299b89e444694456bb7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0d845c92469395061b63ec4955caa608"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xsecure__aes__core__hw_8h.html#a0d845c92469395061b63ec4955caa608">XSECURE_AES_USER_KEY_6_0_OFFSET</a>&#160;&#160;&#160;(0x000001D0U)</td></tr>
<tr class="memdesc:a0d845c92469395061b63ec4955caa608"><td class="mdescLeft">&#160;</td><td class="mdescRight">AES_USER_KEY_6_0 register offset.  <a href="#a0d845c92469395061b63ec4955caa608">More...</a><br/></td></tr>
<tr class="separator:a0d845c92469395061b63ec4955caa608"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa03d53eeaa863e692eefe96330d65a58"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xsecure__aes__core__hw_8h.html#aa03d53eeaa863e692eefe96330d65a58">XSECURE_AES_USER_KEY_7_0_OFFSET</a>&#160;&#160;&#160;(0x000001F0U)</td></tr>
<tr class="memdesc:aa03d53eeaa863e692eefe96330d65a58"><td class="mdescLeft">&#160;</td><td class="mdescRight">AES_USER_KEY_7_0 register offset.  <a href="#aa03d53eeaa863e692eefe96330d65a58">More...</a><br/></td></tr>
<tr class="separator:aa03d53eeaa863e692eefe96330d65a58"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">AES_STATUS register</div></td></tr>
<tr class="memitem:a76af3e62bb4e0c953bcc9cc7643f0f81"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xsecure__aes__core__hw_8h.html#a76af3e62bb4e0c953bcc9cc7643f0f81">XSECURE_AES_STATUS_OFFSET</a>&#160;&#160;&#160;(0x00000000U)</td></tr>
<tr class="memdesc:a76af3e62bb4e0c953bcc9cc7643f0f81"><td class="mdescLeft">&#160;</td><td class="mdescRight">&lt; AES_STATUS register offset and definitions  <a href="#a76af3e62bb4e0c953bcc9cc7643f0f81">More...</a><br/></td></tr>
<tr class="separator:a76af3e62bb4e0c953bcc9cc7643f0f81"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a40dd10f747463d6addf31a5d4f9568b3"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a40dd10f747463d6addf31a5d4f9568b3"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSECURE_AES_STATUS_CM_ENABLED_SHIFT</b>&#160;&#160;&#160;(12U)</td></tr>
<tr class="separator:a40dd10f747463d6addf31a5d4f9568b3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:abe98893bf2adacc839f65fbe36e5734e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="abe98893bf2adacc839f65fbe36e5734e"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSECURE_AES_STATUS_CM_ENABLED_MASK</b>&#160;&#160;&#160;(0x00001000U)</td></tr>
<tr class="separator:abe98893bf2adacc839f65fbe36e5734e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8eb6acb13fbe9124cc1ab378b7d3d0af"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a8eb6acb13fbe9124cc1ab378b7d3d0af"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSECURE_AES_STATUS_BLK_KEY_DEC_DONE_MASK</b>&#160;&#160;&#160;(0x00000020U)</td></tr>
<tr class="separator:a8eb6acb13fbe9124cc1ab378b7d3d0af"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad54a8b2ad88c08707639b0da512999ab"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ad54a8b2ad88c08707639b0da512999ab"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSECURE_AES_STATUS_KEY_INIT_DONE_MASK</b>&#160;&#160;&#160;(0x00000010U)</td></tr>
<tr class="separator:ad54a8b2ad88c08707639b0da512999ab"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:abebf6581c193616182b387184156b06d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="abebf6581c193616182b387184156b06d"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSECURE_AES_STATUS_GCM_TAG_PASS_MASK</b>&#160;&#160;&#160;(0x00000008U)</td></tr>
<tr class="separator:abebf6581c193616182b387184156b06d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5264180b20c4edb8f73fd78ec46295b9"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a5264180b20c4edb8f73fd78ec46295b9"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSECURE_AES_STATUS_DONE_MASK</b>&#160;&#160;&#160;(0x00000004U)</td></tr>
<tr class="separator:a5264180b20c4edb8f73fd78ec46295b9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">AES_KEY_LOAD register</div></td></tr>
<tr class="memitem:a8cdc0ab0e9056621876eed6471b3c7e0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xsecure__aes__core__hw_8h.html#a8cdc0ab0e9056621876eed6471b3c7e0">XSECURE_AES_KEY_LOAD_OFFSET</a>&#160;&#160;&#160;(0x00000008U)</td></tr>
<tr class="memdesc:a8cdc0ab0e9056621876eed6471b3c7e0"><td class="mdescLeft">&#160;</td><td class="mdescRight">&lt; AES_KEY_LOAD register offset and definitions  <a href="#a8cdc0ab0e9056621876eed6471b3c7e0">More...</a><br/></td></tr>
<tr class="separator:a8cdc0ab0e9056621876eed6471b3c7e0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a055be7b8c7afc6777b644f16b8eee441"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a055be7b8c7afc6777b644f16b8eee441"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSECURE_AES_KEY_LOAD_VAL_MASK</b>&#160;&#160;&#160;(0x00000001U)</td></tr>
<tr class="separator:a055be7b8c7afc6777b644f16b8eee441"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">AES_START_MSG register</div></td></tr>
<tr class="memitem:a4adffade0df33cc9209f3765eb8110c2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xsecure__aes__core__hw_8h.html#a4adffade0df33cc9209f3765eb8110c2">XSECURE_AES_START_MSG_OFFSET</a>&#160;&#160;&#160;(0x0000000CU)</td></tr>
<tr class="memdesc:a4adffade0df33cc9209f3765eb8110c2"><td class="mdescLeft">&#160;</td><td class="mdescRight">&lt; AES_START_MSG register offset and definitions  <a href="#a4adffade0df33cc9209f3765eb8110c2">More...</a><br/></td></tr>
<tr class="separator:a4adffade0df33cc9209f3765eb8110c2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a614945873a1f2e293d0b481a4ba3dd34"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a614945873a1f2e293d0b481a4ba3dd34"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSECURE_AES_START_MSG_VAL_MASK</b>&#160;&#160;&#160;(0x00000001U)</td></tr>
<tr class="separator:a614945873a1f2e293d0b481a4ba3dd34"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">AES_MODE register</div></td></tr>
<tr class="memitem:a644c6f57bb1c3442e911588112457c95"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xsecure__aes__core__hw_8h.html#a644c6f57bb1c3442e911588112457c95">XSECURE_AES_MODE_OFFSET</a>&#160;&#160;&#160;(0x00000018U)</td></tr>
<tr class="memdesc:a644c6f57bb1c3442e911588112457c95"><td class="mdescLeft">&#160;</td><td class="mdescRight">&lt; AES_MODE register offset and definitions  <a href="#a644c6f57bb1c3442e911588112457c95">More...</a><br/></td></tr>
<tr class="separator:a644c6f57bb1c3442e911588112457c95"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aecfaab2eac486e58fa87b9f91ec64782"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aecfaab2eac486e58fa87b9f91ec64782"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSECURE_AES_MODE_ENC</b>&#160;&#160;&#160;(0x00000001U)</td></tr>
<tr class="separator:aecfaab2eac486e58fa87b9f91ec64782"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af74efd37e891d3f1831ab8698b8beb31"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="af74efd37e891d3f1831ab8698b8beb31"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSECURE_AES_MODE_DEC</b>&#160;&#160;&#160;(0x00000000U)</td></tr>
<tr class="separator:af74efd37e891d3f1831ab8698b8beb31"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">AES_KUP_WR register</div></td></tr>
<tr class="memitem:a946b1ce12dd72dc6ac6d6f887e87b202"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xsecure__aes__core__hw_8h.html#a946b1ce12dd72dc6ac6d6f887e87b202">XSECURE_AES_KUP_WR_OFFSET</a>&#160;&#160;&#160;(0x0000001CU)</td></tr>
<tr class="memdesc:a946b1ce12dd72dc6ac6d6f887e87b202"><td class="mdescLeft">&#160;</td><td class="mdescRight">&lt; AES_KUP_WR register offset and definitions  <a href="#a946b1ce12dd72dc6ac6d6f887e87b202">More...</a><br/></td></tr>
<tr class="separator:a946b1ce12dd72dc6ac6d6f887e87b202"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:adbeedea7cd005612f3c0d122e8a59903"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="adbeedea7cd005612f3c0d122e8a59903"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSECURE_AES_KUP_WR_IV_SAVE_MASK</b>&#160;&#160;&#160;(0x00000002U)</td></tr>
<tr class="separator:adbeedea7cd005612f3c0d122e8a59903"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aaa84132f0868333dbc0049745a1ca8ec"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aaa84132f0868333dbc0049745a1ca8ec"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSECURE_AES_KUP_WR_KEY_SAVE_MASK</b>&#160;&#160;&#160;(0x00000001U)</td></tr>
<tr class="separator:aaa84132f0868333dbc0049745a1ca8ec"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">AES_KEY_DEC register</div></td></tr>
<tr class="memitem:a914278021d68bfc3552a2c25b0aa1686"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xsecure__aes__core__hw_8h.html#a914278021d68bfc3552a2c25b0aa1686">XSECURE_AES_KEY_DEC_OFFSET</a>&#160;&#160;&#160;(0x00000058U)</td></tr>
<tr class="memdesc:a914278021d68bfc3552a2c25b0aa1686"><td class="mdescLeft">&#160;</td><td class="mdescRight">&lt; AES_KEY_DEC register offset and definitions  <a href="#a914278021d68bfc3552a2c25b0aa1686">More...</a><br/></td></tr>
<tr class="separator:a914278021d68bfc3552a2c25b0aa1686"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aec1748563ccb65afeeee278eec3d1fbd"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aec1748563ccb65afeeee278eec3d1fbd"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSECURE_AES_KEY_DEC_MASK</b>&#160;&#160;&#160;(0xFFFFFFFFU)</td></tr>
<tr class="separator:aec1748563ccb65afeeee278eec3d1fbd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4c4a25d02bc5b21d457409942d199b49"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a4c4a25d02bc5b21d457409942d199b49"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSECURE_AES_KEY_DEC_RESET_MASK</b>&#160;&#160;&#160;(0X00000000U)</td></tr>
<tr class="separator:a4c4a25d02bc5b21d457409942d199b49"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">AES_KEY_ZEROED_STATUS register</div></td></tr>
<tr class="memitem:ac3523a3792127cae78e3f9b98ea9edea"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xsecure__aes__core__hw_8h.html#ac3523a3792127cae78e3f9b98ea9edea">XSECURE_AES_KEY_ZEROED_STATUS_OFFSET</a>&#160;&#160;&#160;(0x00000064U)</td></tr>
<tr class="memdesc:ac3523a3792127cae78e3f9b98ea9edea"><td class="mdescLeft">&#160;</td><td class="mdescRight">&lt; AES_KEY_ZEROED_STATUS register offset and definitions  <a href="#ac3523a3792127cae78e3f9b98ea9edea">More...</a><br/></td></tr>
<tr class="separator:ac3523a3792127cae78e3f9b98ea9edea"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a40b7f938bc254e7a699d2fb516b2396d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a40b7f938bc254e7a699d2fb516b2396d"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSECURE_PUF_KEY_ZEROED_MASK</b>&#160;&#160;&#160;(0x200000U)</td></tr>
<tr class="separator:a40b7f938bc254e7a699d2fb516b2396d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">AES_CM_EN register</div></td></tr>
<tr class="memitem:a3dd8162ca2b2174c50dfb7e3bbdab09f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xsecure__aes__core__hw_8h.html#a3dd8162ca2b2174c50dfb7e3bbdab09f">XSECURE_AES_CM_EN_OFFSET</a>&#160;&#160;&#160;(0x0000007CU)</td></tr>
<tr class="memdesc:a3dd8162ca2b2174c50dfb7e3bbdab09f"><td class="mdescLeft">&#160;</td><td class="mdescRight">&lt; AES_CM_EN register offset and definitions  <a href="#a3dd8162ca2b2174c50dfb7e3bbdab09f">More...</a><br/></td></tr>
<tr class="separator:a3dd8162ca2b2174c50dfb7e3bbdab09f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ace59952e0daf836fffe4e4cd3b7d080e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ace59952e0daf836fffe4e4cd3b7d080e"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSECURE_AES_CM_EN_VAL_MASK</b>&#160;&#160;&#160;(0x00000001U)</td></tr>
<tr class="separator:ace59952e0daf836fffe4e4cd3b7d080e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">AES_SPLIT_CFG register</div></td></tr>
<tr class="memitem:a5a5346e407a7e0dc27a57ed9b4007d9c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xsecure__aes__core__hw_8h.html#a5a5346e407a7e0dc27a57ed9b4007d9c">XSECURE_AES_SPLIT_CFG_OFFSET</a>&#160;&#160;&#160;(0x00000080U)</td></tr>
<tr class="memdesc:a5a5346e407a7e0dc27a57ed9b4007d9c"><td class="mdescLeft">&#160;</td><td class="mdescRight">&lt; AES_SPLIT_CFG register offset and definitions  <a href="#a5a5346e407a7e0dc27a57ed9b4007d9c">More...</a><br/></td></tr>
<tr class="separator:a5a5346e407a7e0dc27a57ed9b4007d9c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a519512b083a4c90e376df6b0849fe7b1"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a519512b083a4c90e376df6b0849fe7b1"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSECURE_AES_SPLIT_CFG_KEY_SPLIT</b>&#160;&#160;&#160;(0x00000002U)</td></tr>
<tr class="separator:a519512b083a4c90e376df6b0849fe7b1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad77478866bf001725cfb0effce624553"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ad77478866bf001725cfb0effce624553"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSECURE_AES_SPLIT_CFG_DATA_SPLIT</b>&#160;&#160;&#160;(0x00000001U)</td></tr>
<tr class="separator:ad77478866bf001725cfb0effce624553"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a870d8ab66ab94243d83cbb9a16905092"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a870d8ab66ab94243d83cbb9a16905092"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSECURE_AES_SPLIT_CFG_DATA_KEY_DISABLE</b>&#160;&#160;&#160;(0U)</td></tr>
<tr class="separator:a870d8ab66ab94243d83cbb9a16905092"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">AES_DATA_SWAP register</div></td></tr>
<tr class="memitem:ac14b72a31d6841f368eb38d4104531e9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xsecure__aes__core__hw_8h.html#ac14b72a31d6841f368eb38d4104531e9">XSECURE_AES_DATA_SWAP_OFFSET</a>&#160;&#160;&#160;(0x00000084U)</td></tr>
<tr class="memdesc:ac14b72a31d6841f368eb38d4104531e9"><td class="mdescLeft">&#160;</td><td class="mdescRight">&lt; AES_DATA_SWAP register offset and definitions  <a href="#ac14b72a31d6841f368eb38d4104531e9">More...</a><br/></td></tr>
<tr class="separator:ac14b72a31d6841f368eb38d4104531e9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a027df23de44f04573f22bb0771136a17"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a027df23de44f04573f22bb0771136a17"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSECURE_AES_DATA_SWAP_VAL_MASK</b>&#160;&#160;&#160;(0x00000001U)</td></tr>
<tr class="separator:a027df23de44f04573f22bb0771136a17"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad3f9e1398bccf1512260d5c3e92a875b"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ad3f9e1398bccf1512260d5c3e92a875b"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSECURE_AES_DATA_SWAP_VAL_DISABLE</b>&#160;&#160;&#160;(0x00000000U)</td></tr>
<tr class="separator:ad3f9e1398bccf1512260d5c3e92a875b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">SECURITY_MISC_1 register in EFUSE_CACHE module</div></td></tr>
<tr class="memitem:abdca87de2b9410a316e548b9350a2968"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xsecure__aes__core__hw_8h.html#abdca87de2b9410a316e548b9350a2968">XSECURE_EFUSE_SECURITY_MISC1</a>&#160;&#160;&#160;(0xF12500E8U)</td></tr>
<tr class="memdesc:abdca87de2b9410a316e548b9350a2968"><td class="mdescLeft">&#160;</td><td class="mdescRight">&lt; SECURITY_MISC_1 register offset and definitions  <a href="#abdca87de2b9410a316e548b9350a2968">More...</a><br/></td></tr>
<tr class="separator:abdca87de2b9410a316e548b9350a2968"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2d84cd5dbb844e20dd6d93aa57692607"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a2d84cd5dbb844e20dd6d93aa57692607"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSECURE_EFUSE_DPA_CM_DIS_MASK</b>&#160;&#160;&#160;(0xFFFF0000U)</td></tr>
<tr class="separator:a2d84cd5dbb844e20dd6d93aa57692607"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
<h2 class="groupheader">Macro Definition Documentation</h2>
<a class="anchor" id="ab30dfee1aa8df3062aa88d5a37534eda"></a>
<div class="memitem">
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          <td class="memname">#define XSECURE_AES_AAD_OFFSET&#160;&#160;&#160;(0x0000006CU)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AES_AAD register offset. </p>

</div>
</div>
<a class="anchor" id="a523043b9b41cd0567bf865bc996fa404"></a>
<div class="memitem">
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          <td class="memname">#define XSECURE_AES_BH_KEY_0_OFFSET&#160;&#160;&#160;(0x000000F0U)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AES_BH_KEY_0 register offset. </p>

</div>
</div>
<a class="anchor" id="a3dd8162ca2b2174c50dfb7e3bbdab09f"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XSECURE_AES_CM_EN_OFFSET&#160;&#160;&#160;(0x0000007CU)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>&lt; AES_CM_EN register offset and definitions </p>

</div>
</div>
<a class="anchor" id="ac14b72a31d6841f368eb38d4104531e9"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XSECURE_AES_DATA_SWAP_OFFSET&#160;&#160;&#160;(0x00000084U)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>&lt; AES_DATA_SWAP register offset and definitions </p>

<p>Referenced by <a class="el" href="group__xsecure__aes__server__apis.html#ga6422d39ce630dc928daba92a65da4c56">XSecure_AesEcbDecrypt()</a>, and <a class="el" href="group__xsecure__aes__server__apis.html#ga4da9ead453ef1dbeebefeebb377eb94d">XSecure_AesKeyUnwrap()</a>.</p>

</div>
</div>
<a class="anchor" id="a7af708c3a88350c17329dc3d43ec674a"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XSECURE_AES_IV_0_OFFSET&#160;&#160;&#160;(0x00000040U)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AES_IV_0 register offset. </p>

</div>
</div>
<a class="anchor" id="a7cb9fb7cebf2d5bbaafe1b724080f6ad"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XSECURE_AES_IV_3_OFFSET&#160;&#160;&#160;(0x0000004CU)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AES_IV_3 register offset. </p>

</div>
</div>
<a class="anchor" id="a914278021d68bfc3552a2c25b0aa1686"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XSECURE_AES_KEY_DEC_OFFSET&#160;&#160;&#160;(0x00000058U)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>&lt; AES_KEY_DEC register offset and definitions </p>

</div>
</div>
<a class="anchor" id="a1b97c95e93272e98ea09c3c092c55b4d"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XSECURE_AES_KEY_DEC_SEL_OFFSET&#160;&#160;&#160;(0x00000060U)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AES_KEY_DEC_SEL register offset. </p>

</div>
</div>
<a class="anchor" id="a1df2fa073c3d742d262613a8ea0c0a50"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XSECURE_AES_KEY_DEC_TRIG_OFFSET&#160;&#160;&#160;(0x0000005CU)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AES_KEY_DEC_TRIG register offset. </p>

</div>
</div>
<a class="anchor" id="a8cdc0ab0e9056621876eed6471b3c7e0"></a>
<div class="memitem">
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          <td class="memname">#define XSECURE_AES_KEY_LOAD_OFFSET&#160;&#160;&#160;(0x00000008U)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>&lt; AES_KEY_LOAD register offset and definitions </p>

</div>
</div>
<a class="anchor" id="a032b21f266f931960dc0fab1c6df15ca"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XSECURE_AES_KEY_SEL_OFFSET&#160;&#160;&#160;(0x00000004U)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AES_KEY_SEL register offset. </p>

</div>
</div>
<a class="anchor" id="a4eeb401134c2a56c8a82b0cc0eca3f55"></a>
<div class="memitem">
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          <td class="memname">#define XSECURE_AES_KEY_SIZE_OFFSET&#160;&#160;&#160;(0x00000050U)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AES_KEY_SIZE register offset. </p>

</div>
</div>
<a class="anchor" id="ac3523a3792127cae78e3f9b98ea9edea"></a>
<div class="memitem">
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          <td class="memname">#define XSECURE_AES_KEY_ZEROED_STATUS_OFFSET&#160;&#160;&#160;(0x00000064U)</td>
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      </table>
</div><div class="memdoc">

<p>&lt; AES_KEY_ZEROED_STATUS register offset and definitions </p>
<p>AES_KEY_ZEROED register offset </p>

</div>
</div>
<a class="anchor" id="a946b1ce12dd72dc6ac6d6f887e87b202"></a>
<div class="memitem">
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          <td class="memname">#define XSECURE_AES_KUP_WR_OFFSET&#160;&#160;&#160;(0x0000001CU)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>&lt; AES_KUP_WR register offset and definitions </p>

</div>
</div>
<a class="anchor" id="a644c6f57bb1c3442e911588112457c95"></a>
<div class="memitem">
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          <td class="memname">#define XSECURE_AES_MODE_OFFSET&#160;&#160;&#160;(0x00000018U)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>&lt; AES_MODE register offset and definitions </p>

</div>
</div>
<a class="anchor" id="aafd28b72f9ee5ce4fa83e3e27d3410d8"></a>
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          <td class="memname">#define XSECURE_AES_SOFT_RST_OFFSET&#160;&#160;&#160;(0x00000010U)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AES_KEY_SOFT_RST register offset. </p>

<p>Referenced by <a class="el" href="group__xsecure__aes__server__apis.html#ga6422d39ce630dc928daba92a65da4c56">XSecure_AesEcbDecrypt()</a>, <a class="el" href="group__xsecure__aes__server__apis.html#ga4da9ead453ef1dbeebefeebb377eb94d">XSecure_AesKeyUnwrap()</a>, and <a class="el" href="group__xsecure__generic__server__apis.html#ga07ca644998ec3bcf61557b4510708101">XSecure_SetDataContextLost()</a>.</p>

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<a class="anchor" id="a5a5346e407a7e0dc27a57ed9b4007d9c"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XSECURE_AES_SPLIT_CFG_OFFSET&#160;&#160;&#160;(0x00000080U)</td>
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      </table>
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<p>&lt; AES_SPLIT_CFG register offset and definitions </p>

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<a class="anchor" id="a4adffade0df33cc9209f3765eb8110c2"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XSECURE_AES_START_MSG_OFFSET&#160;&#160;&#160;(0x0000000CU)</td>
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<p>&lt; AES_START_MSG register offset and definitions </p>

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<a class="anchor" id="a76af3e62bb4e0c953bcc9cc7643f0f81"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XSECURE_AES_STATUS_OFFSET&#160;&#160;&#160;(0x00000000U)</td>
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      </table>
</div><div class="memdoc">

<p>&lt; AES_STATUS register offset and definitions </p>

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<a class="anchor" id="a5004b736c625abef0ca6dada14dcc962"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XSECURE_AES_USER_KEY_0_0_OFFSET&#160;&#160;&#160;(0x00000110U)</td>
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</div><div class="memdoc">

<p>AES_USER_KEY_0_0 register offset. </p>

</div>
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<a class="anchor" id="a63c576fa7f9355d7dbcaa5c96707c105"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XSECURE_AES_USER_KEY_1_0_OFFSET&#160;&#160;&#160;(0x00000130U)</td>
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<p>AES_USER_KEY_1_0 register offset. </p>

</div>
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<a class="anchor" id="a06ffdf0ece06ce79887a77fe4544aeb8"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XSECURE_AES_USER_KEY_2_0_OFFSET&#160;&#160;&#160;(0x00000150U)</td>
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<p>AES_USER_KEY_2_0 register offset. </p>

</div>
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<a class="anchor" id="a3786274cb3729c28c6e2fffd1444a60d"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XSECURE_AES_USER_KEY_3_0_OFFSET&#160;&#160;&#160;(0x00000170U)</td>
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<p>AES_USER_KEY_3_0 register offset. </p>

</div>
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<a class="anchor" id="a927532a3705a2716f07c4ddf272b1097"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XSECURE_AES_USER_KEY_4_0_OFFSET&#160;&#160;&#160;(0x00000190U)</td>
        </tr>
      </table>
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<p>AES_USER_KEY_4_0 register offset. </p>

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<a class="anchor" id="a35b6c109e77ba299b89e444694456bb7"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XSECURE_AES_USER_KEY_5_0_OFFSET&#160;&#160;&#160;(0x000001B0U)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AES_USER_KEY_5_0 register offset. </p>

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<a class="anchor" id="a0d845c92469395061b63ec4955caa608"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSECURE_AES_USER_KEY_6_0_OFFSET&#160;&#160;&#160;(0x000001D0U)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AES_USER_KEY_6_0 register offset. </p>

</div>
</div>
<a class="anchor" id="aa03d53eeaa863e692eefe96330d65a58"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSECURE_AES_USER_KEY_7_0_OFFSET&#160;&#160;&#160;(0x000001F0U)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AES_USER_KEY_7_0 register offset. </p>

</div>
</div>
<a class="anchor" id="abdca87de2b9410a316e548b9350a2968"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XSECURE_EFUSE_SECURITY_MISC1&#160;&#160;&#160;(0xF12500E8U)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>&lt; SECURITY_MISC_1 register offset and definitions </p>

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